SDC Clock Explorer | 看懂每一条时钟约束

本地官方示例：不会调用 API，也不会消耗次数。

SDC 源码

UTF-832 LINES 已解析

# SoC top-level clock constraints
create_clock -name SYS_CLK -period 10.000 \
  -waveform {0.000 5.000} [get_ports sys_clk_i]

create_generated_clock -name CPU_CLK \
  -master_clock SYS_CLK -source [get_ports sys_clk_i] \
  -divide_by 2 [get_pins u_clk_div/cpu_clk_o]

create_generated_clock -name BUS_CLK \
  -master_clock CPU_CLK -source [get_pins u_clk_div/cpu_clk_o] \
  -divide_by 2 [get_pins u_clk_div/bus_clk_o]

create_generated_clock -name DBG_CLK \
  -master_clock SYS_CLK -source [get_ports sys_clk_i] \
  -divide_by 8 [get_pins u_dbg/clk_o]

create_clock -name EXT_REF -period 20.000 [get_ports ref_clk_i]

create_generated_clock -name PIXEL_CLK \
  -master_clock EXT_REF -source [get_ports ref_clk_i] \
  -multiply_by 3 [get_pins u_display/pixel_clk_o]

set_clock_groups -asynchronous \
  -group {SYS_CLK CPU_CLK BUS_CLK DBG_CLK} \
  -group {EXT_REF PIXEL_CLK}

create_generated_clock -name AUX_CLK \
  -source [get_pins missing/pll_o] -divide_by 4 \
  [get_pins u_aux/clk_o]

# Vendor extension retained as unsupported
set_clock_tree_options -target_skew 0.08 [get_clocks SYS_CLK]

约束拓扑 LOGICAL VIEW

7/7 可见

主时钟派生未解析